vivado implementation執行時候報錯：Unsupported PLLE2_ADV connectivity.......
執行時候出錯， [DRC REQP-1712] Input clock driver: Unsupported PLLE2_ADV connectivity. The signal u_clk_wi ...
花費 5 ms
執行時候出錯， [DRC REQP-1712] Input clock driver: Unsupported PLLE2_ADV connectivity. The signal u_clk_wi ...